Discussion:
Soft Switches vs Bitmapped Registers
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Zach Z
2018-02-03 01:32:06 UTC
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Why does the Apple II use softswitches which are agnostic to what is written to them instead of combining eight of these "ON/OFF Switches" into a single bitmapped register? Each register contains eight bits which can be set to 1 or 0 depending if the "switch" is on or off. Instead of using two memory locations so turn one thing on or off, eight things can be controlled from a single memory location using 1/16 the required address space which was already at a premium.
Anthony Ortiz
2018-02-03 01:57:38 UTC
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My guess is that it's because most of these are special locations that don't really hold a value at all, but I'd love if someone with more knowledge could elaborate on this.
Michael J. Mahon
2018-02-03 03:00:27 UTC
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Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Anthony Ortiz
2018-02-03 03:27:21 UTC
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Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Definitely. If Woz gave it any thought at all I'd imagine he decided against it because if he packed the bits then you'd have the additional worry and expense of not disturbing those bits; that is, you'd need to mask those bits every time you set or cleared your bit.
James Davis
2018-02-03 03:29:46 UTC
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Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Yes, the KISS method. Also, might take more time (cycles) to deal with bit decoding from assembly/firmware code.
Zach Z
2018-02-03 04:05:41 UTC
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Post by James Davis
Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Yes, the KISS method. Also, might take more time (cycles) to deal with bit decoding from assembly/firmware code.
I believe even the Disk II controller uses eight bytes to control the stepper motor which should just take two bits in a control register


0x = No Step
10 = Step In
11 = Step Out

(x = don't care)
awanderin
2018-02-03 06:47:36 UTC
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Post by Zach Z
Post by James Davis
Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Yes, the KISS method. Also, might take more time (cycles) to deal
with bit decoding from assembly/firmware code.
I believe even the Disk II controller uses eight bytes to control the
stepper motor which should just take two bits in a control register
0x = No Step
10 = Step In
11 = Step Out
(x = don't care)
It takes more logic chips to do this. As others have alluded above, Woz
chose the lower-part-count solution. One decoder chip, such as a 74LS138
3-to-8 decoder, controls eight soft-switches. If you feed address lines
A3, A2, and A1 to it, and use A0 to control OFF and ON, you have the
video soft-switches decoded with one chip. See how many chips it would
take with one address. (I haven't yet.)
--
--
Jerry awanderin at gmail dot com
Zach Z
2018-02-03 19:45:01 UTC
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Post by awanderin
Post by Zach Z
Post by James Davis
Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Yes, the KISS method. Also, might take more time (cycles) to deal
with bit decoding from assembly/firmware code.
I believe even the Disk II controller uses eight bytes to control the
stepper motor which should just take two bits in a control register
0x = No Step
10 = Step In
11 = Step Out
(x = don't care)
It takes more logic chips to do this. As others have alluded above, Woz
chose the lower-part-count solution. One decoder chip, such as a 74LS138
3-to-8 decoder, controls eight soft-switches. If you feed address lines
A3, A2, and A1 to it, and use A0 to control OFF and ON, you have the
video soft-switches decoded with one chip. See how many chips it would
take with one address. (I haven't yet.)
--
--
Jerry awanderin at gmail dot com
So, Maximizing the amount of directly addressable RAM the machine can have was not a design choice. It did not matter if bank switching was necessary to allow for nearly a full 64K RAM. Is that true?
Michael J. Mahon
2018-02-04 16:56:26 UTC
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Post by Zach Z
Post by awanderin
Post by Zach Z
Post by James Davis
Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Yes, the KISS method. Also, might take more time (cycles) to deal
with bit decoding from assembly/firmware code.
I believe even the Disk II controller uses eight bytes to control the
stepper motor which should just take two bits in a control register
0x = No Step
10 = Step In
11 = Step Out
(x = don't care)
It takes more logic chips to do this. As others have alluded above, Woz
chose the lower-part-count solution. One decoder chip, such as a 74LS138
3-to-8 decoder, controls eight soft-switches. If you feed address lines
A3, A2, and A1 to it, and use A0 to control OFF and ON, you have the
video soft-switches decoded with one chip. See how many chips it would
take with one address. (I haven't yet.)
--
--
Jerry awanderin at gmail dot com
So, Maximizing the amount of directly addressable RAM the machine can
have was not a design choice. It did not matter if bank switching was
necessary to allow for nearly a full 64K RAM. Is that true?
The 6502 requires I/O to be memory-mapped.

Once the decision was made to allocate $Cxxx to memory-mapped I/O, the size
of non-bank-switched memory was fixed. Suballocation of the I/O addresses
has no effect on addressable RAM, and suballocation is not terribly
space-constrained.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Scott Alfter
2018-02-06 16:02:39 UTC
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Post by Zach Z
So, Maximizing the amount of directly addressable RAM the machine can
have was not a design choice. It did not matter if bank switching was
necessary to allow for nearly a full 64K RAM. Is that true?
When the Apple II was introduced in 1977, I think it was available with as
little as 4K RAM. You could've gotten it with as much as 48K, but this was
obscenely expensive at the time. Throwing a bit of address space (only 256
bytes, half for the motherboard and the other half split across 8 slots) at
I/O was a cheaper solution than the alternative, and there was still more
than enough space for RAM.

It also simplifies the software side of things. Want to wait until a key's
been pressed? Read the keyboard register and loop until the negative flag
is set. Two instructions, five bytes...and the key that was pressed is
already in the lower 7 bits of the accumulator. If the "key's-been-pressed"
bit had been shoehorned in with a bunch of other flag bits, you'd need to
read a value, mask it to get the bit you want, branch until the bit's set,
and then read the character that was pressed from someplace else. At a
minimum, I'm guessing four instructions and 10 bytes. Twice as much code,
and who knows how much more logic to make it happen.

_/_
/ v \ Scott Alfter (remove the obvious to send mail)
(IIGS( https://alfter.us/ Top-posting!
\_^_/ >What's the most annoying thing on Usenet?
Gordon Henderson
2018-02-03 07:02:01 UTC
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Post by James Davis
Post by Michael J. Mahon
Post by Anthony Ortiz
My guess is that it's because most of these are special locations that
don't really hold a value at all, but I'd love if someone with more
knowledge could elaborate on this.
Given Woz' proclivities, I'd bet that he chose the simplest implementation.
Yes, the KISS method. Also, might take more time (cycles) to deal with bit decoding
from assembly/firmware code.
Even more from BASIC... Then there's the whole read/modify/write thing,
so requires the data bus (and more PCB tracking) to be involved too... But
decode the address lines and feed them into a flip flop.. simples.

Gordon
I am Rob
2018-02-03 02:25:13 UTC
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Post by Zach Z
Why does the Apple II use softswitches which are agnostic to what is written to them instead of combining eight of these "ON/OFF Switches" into a single bitmapped register? Each register contains eight bits which can be set to 1 or 0 depending if the "switch" is on or off. Instead of using two memory locations so turn one thing on or off, eight things can be controlled from a single memory location using 1/16 the required address space which was already at a premium.
Switches are just that. To flip a switch, a circuit is either pulled high or low. This can be shown using a negative result or a positive result which is what the hi-bit does.
Patrick Schaefer
2018-02-03 10:36:18 UTC
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Post by Zach Z
Why does the Apple II use softswitches which are agnostic to what is
written to them instead of combining eight of these "ON/OFF Switches"
into a single bitmapped register?
The scheme Apple called "soft switch" requires decoding of the address
lines. For a bitwise implementation, you would have to decode the data
lines, too. No problem within an ASIC, but the Apple II uses discrete
logic.

Software is the next issue. With indexed adressing, it is easy to access
one out of n consecutive memory locations. Reading, modifying and
writing back a register takes more time.


Patrick
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