Post by Anthony Ortiz Post by Michael J. Mahon
It's not AE. Cache technology for the Apple II was developed first for the
SpeedDemon plug-in card, and later applied by the same folks in the Zip
Apple eventually adopted the Zip Chip design (but not packaging) for the
TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
less elegant solution than caching, since smaller SRAMs can always be made
faster than large ones (which is why multi-level caches are now universal).
The card/multi-chip package detects accesses to certain I/O addresses, like
slot 6, and then runs synchronously with the 1MHz clock for a certain
length of time. Since the timing-critical code regularly accesses /DEVSEL
addresses, the processor remains slowed down until (in the case of slots)
about 50 milliseconds after the last access to a "slow" address.
This is documented in the Zip Chip documentation text file on the utility
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Wow, thanks Michael! They don't call you the "Woz Humbler" for nothing!
:P A friend of mine and I didn't know how they did it, so I thought about
it a bit and figured that if I had to do this myself I would synchronize
to the slow clock until x amount of time from the last access to a slow
location, so I'm happy that we came about the same solution.
They must synchronize to the same 1mhz clock right? Otherwise I don't see
how they would get an exact match since Apple does that elongated cycle
thing every 65th cycle. I figure the various DOS's must factor that
elongated cycle into their timings, but I don't know anything about that
subject yet as my Beneath Apple DOS and ProDos books have yet to arrive.
It's even simpler.