Discussion:
Transwarp - How do they work?
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Anthony Ortiz
2017-07-08 14:35:55 UTC
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I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
John Brooks
2017-07-08 23:56:58 UTC
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Post by Anthony Ortiz
I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
The Transwarp & Zip accelerators plug into the CPU socket, replacing the original CPU.

Since the accelerator board contains it's own faster CPU, and there is no longer a CPU on the motherboard, there is no problem 'taking over completely'.

-JB
@JBrooksBSI
geoff body
2017-07-09 00:31:15 UTC
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For the slot based accelerators which don't use the CPU socket, it is most likely they are using the DMA signal to disable the on board 6502. This allows the 6502/65c02 on the card to control the system. This can limit the use of other DMA based cards in the system.

Regards
Geoff B
Anthony Ortiz
2017-07-09 00:34:04 UTC
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Post by geoff body
For the slot based accelerators which don't use the CPU socket, it is most likely they are using the DMA signal to disable the on board 6502. This allows the 6502/65c02 on the card to control the system. This can limit the use of other DMA based cards in the system.
Regards
Geoff B
Yes, it seems DMA is how it's accomplishing the disabling of the on-board CPU. I happened to come across some info on it earlier today but you and Michael Mahon (who messaged me privately) are indeed correct.

Thanks!
STYNX
2017-07-09 17:07:51 UTC
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Post by Anthony Ortiz
I've searched for information on how the Transwarps actually work but can only find the manual and some repair info. What I would like to understand is how it's able to not only intercept the on-board CPU but take over completely, preventing the on-board CPU from operating. Does anyone have any knowledge in this area?
There are 2 concepts being used in Apple II accelerators.

1. Caching
2. Shadowing

The ZIP CHIP and McT SpeedDemon use caching and all other accelerator use shadowing.

Caching is 'relatively' simple. It has a small full speed cache-memory that allows full speed access for data that has already been read at least once. Every memory-write is done into the cache as well as the A2-memory (there may be some exceptions like the zero-page). Reading a byte can be done from the cache at full speed or from the memory at 1Mhz. Emptying the whole cache is not problematic as it will get filled again by normal usage. The main problem are the rules that map the memory locations to the cache. The zip-chip has 8kb of cache and must map up to 128k of memory locations. This needs highly optimized logic to allow a good acceleration.

Shadowing replaces some memory locations completely with full speed shadow-memory. Some memory locations must be written into the A2-memory (video, text...) and bank switching must be mapped as well. The whole process can get a bit complicated but allows relatively linear acceleration. A memory-shadow must have at least the same amount of memory as the host-system. (128k for the Apple //e)

-Jonas
Anthony Ortiz
2017-07-28 16:01:41 UTC
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This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
Tom Greene
2017-07-28 16:33:54 UTC
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Post by Anthony Ortiz
This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.

Tom
Anthony Ortiz
2017-07-28 17:46:40 UTC
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Post by Tom Greene
Post by Anthony Ortiz
This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.
Tom
Ahhhhh, good one.... that makes sense, for the disk drive at least. I wonder what scheme they used for the serial port and other timing-critical peripherals.
James Davis
2017-07-29 05:43:27 UTC
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Post by Anthony Ortiz
Ahhhhh, good one.... that makes sense, for the disk drive at least. I wonder what scheme they used for the serial port and other timing-critical peripherals.
IIRC, with my Zip-Chip, I could configure it to slow down for any slots I needed it to do so for.
STYNX
2017-07-28 18:30:26 UTC
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Post by Tom Greene
Post by Anthony Ortiz
This brings up another question... how are they able to slow down to 1mhz speeds every time they access the peripherals (ie. memory mapped IO addresses) and maintain that speed during critical timing loops that it may know nothing about (such as disk access code) and speed up to full acceleration the rest of the time? I wonder what happened to those guys at AE, would love to see them in the groups and pick their brain.
For disk access most (if not all?) accelerators watch for access to the disk motor on/motor off soft switches and slow down to 1MHz whenever the drive is spinning.
Tom
There are several memory-locations to be monitored. Speaker and Paddle fro example, to name two. The method to slow down itself is dependent on the developer of the accelerator. You could simply 'stop' the cpu on the accelerator for a part of the 1Mhz cycle or add a delay of a bunch of nanoseconds (200-300ns). If you want to go all out, you can implement a buffer for some memory locations (audio, paddles for example) or even use a dual port memory with intelligent synchronization.

-Jonas
Michael J. Mahon
2017-07-28 20:17:08 UTC
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Post by Anthony Ortiz
This brings up another question... how are they able to slow down to 1mhz
speeds every time they access the peripherals (ie. memory mapped IO
addresses) and maintain that speed during critical timing loops that it
may know nothing about (such as disk access code) and speed up to full
acceleration the rest of the time? I wonder what happened to those guys
at AE, would love to see them in the groups and pick their brain.
It's not AE. Cache technology for the Apple II was developed first for the
SpeedDemon plug-in card, and later applied by the same folks in the Zip
Chip.
Apple eventually adopted the Zip Chip design (but not packaging) for the
IIc+.

TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
less elegant solution than caching, since smaller SRAMs can always be made
faster than large ones (which is why multi-level caches are now universal).


The card/multi-chip package detects accesses to certain I/O addresses, like
slot 6, and then runs synchronously with the 1MHz clock for a certain
length of time. Since the timing-critical code regularly accesses /DEVSEL
addresses, the processor remains slowed down until (in the case of slots)
about 50 milliseconds after the last access to a "slow" address.

This is documented in the Zip Chip documentation text file on the utility
disk.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Anthony Ortiz
2017-07-28 22:50:22 UTC
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Post by Michael J. Mahon
It's not AE. Cache technology for the Apple II was developed first for the
SpeedDemon plug-in card, and later applied by the same folks in the Zip
Chip.
Apple eventually adopted the Zip Chip design (but not packaging) for the
IIc+.
TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
less elegant solution than caching, since smaller SRAMs can always be made
faster than large ones (which is why multi-level caches are now universal).
The card/multi-chip package detects accesses to certain I/O addresses, like
slot 6, and then runs synchronously with the 1MHz clock for a certain
length of time. Since the timing-critical code regularly accesses /DEVSEL
addresses, the processor remains slowed down until (in the case of slots)
about 50 milliseconds after the last access to a "slow" address.
This is documented in the Zip Chip documentation text file on the utility
disk.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Wow, thanks Michael! They don't call you the "Woz Humbler" for nothing! :P A friend of mine and I didn't know how they did it, so I thought about it a bit and figured that if I had to do this myself I would synchronize to the slow clock until x amount of time from the last access to a slow location, so I'm happy that we came about the same solution.

They must synchronize to the same 1mhz clock right? Otherwise I don't see how they would get an exact match since Apple does that elongated cycle thing every 65th cycle. I figure the various DOS's must factor that elongated cycle into their timings, but I don't know anything about that subject yet as my Beneath Apple DOS and ProDos books have yet to arrive.
Michael J. Mahon
2017-07-28 23:34:45 UTC
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Post by Anthony Ortiz
Post by Michael J. Mahon
It's not AE. Cache technology for the Apple II was developed first for the
SpeedDemon plug-in card, and later applied by the same folks in the Zip
Chip.
Apple eventually adopted the Zip Chip design (but not packaging) for the
IIc+.
TransWarps (at least in the beginning) shadowed all of Apple RAM, a much
less elegant solution than caching, since smaller SRAMs can always be made
faster than large ones (which is why multi-level caches are now universal).
The card/multi-chip package detects accesses to certain I/O addresses, like
slot 6, and then runs synchronously with the 1MHz clock for a certain
length of time. Since the timing-critical code regularly accesses /DEVSEL
addresses, the processor remains slowed down until (in the case of slots)
about 50 milliseconds after the last access to a "slow" address.
This is documented in the Zip Chip documentation text file on the utility
disk.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
Wow, thanks Michael! They don't call you the "Woz Humbler" for nothing!
:P A friend of mine and I didn't know how they did it, so I thought about
it a bit and figured that if I had to do this myself I would synchronize
to the slow clock until x amount of time from the last access to a slow
location, so I'm happy that we came about the same solution.
They must synchronize to the same 1mhz clock right? Otherwise I don't see
how they would get an exact match since Apple does that elongated cycle
thing every 65th cycle. I figure the various DOS's must factor that
elongated cycle into their timings, but I don't know anything about that
subject yet as my Beneath Apple DOS and ProDos books have yet to arrive.
It's even simpler.

Transitions in digital systems are driven by clock edges, so if it's time
to run synchronously with the 1MHz clock, you just switch to the slow
clock.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
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