Post by Anthony Ortiz Post by STYNX
It seems to work. I have installed 2 32k sram with 35ns and connected the A13 and A14 lines from the 2 32k sram to the cpu (I soldered some in-between-sockets).
There wasn't any noticeable speedup though.
I wonder how the cache knows not to cache memory-mapped addresses.
There is a tag-ram and the datagram portion of the cache. The tag maps the cached addresses and the data-ram holds the data. By using 3 datelines as address-tag, you can identify which 8k-area address is corresponding to the current 64k-area address. There are 5bits of the tag-data remaining to allow mapping of bank switching and other changes to the memory. With 5bits you can map another 32 possible 64k blocks resulting in 2mb of catchable memory area.
The method itself is not very complicated as you just have to enable the data-memory if the tag-memory has produced a 'hit' (memory location cached). All complicated stuff lies in the logic generation the tag-memory data (3 address bits + 5 mode bits). By using a more recent (after 1990) specialized tag-ram, the logic is reduced to just producing unique mode-patterns to allow caching of the correct memory areas. You would generate a mode-pattern that is not used in the tag-data to prevent caching :-)
Caching itself is only possible, if the memory area was read at least once! Or if a logic is implemented that always caches special memory locations like zero page....