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MMU Soft Switch questions
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Anthony Ortiz
2017-08-23 03:48:01 UTC
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Going through Sather's book and have a few questions...

1) What is meant by odd and even access? Is there some counter from the moment the computer is reset where the first read at an address is considered odd and the second one is even and so on? If so, I guess we'd have to figure out the current value first in order to set it to where we want it. If not, what resets this counter?

2) Double reads - does that mean two consecutive reads, as in I can't even place a NOP in between those reads? I imagine three reads would terminate the effect and four reads would enable the effect again?

3) What constitutes High RAM being enabled? Is it when either HIRAMRD or HIRAMWRT is enabled, or if both are enabled? I ask because on page 130 Sathers states that ALTZP depends on High RAM being enabled to switch over $D000-$FFFF.

4) Is there a particular reason why we need to have HIRAMRD and HIRAMWRT? Why not just have a HIRAM switch that gives you full access when it's set just like any other region of RAM? Is this a feature or the result of some historical oddity?

5) On page 128 Sather's states : "4. When a system reset occurs, all MMU soft switches are reset (turned off). High RAM is disabled for reading and enabled for writing." I was scratching my head wondering why HIRAMWRT' would be enabled after a reset when I realized it's not... I keep forgetting the ['] after HIRAMWRT'. Anyway, my question is, does this mean that when I write to a ROM address it's actually writing to High RAM behind the scenes?
qkumba
2017-08-23 04:03:46 UTC
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Post by Anthony Ortiz
1) What is meant by odd and even access?
The low bit of Address is 1 or 0 (e.g. C089 vs C088).
Post by Anthony Ortiz
2) Double reads - does that mean two consecutive reads, as in I can't even place a NOP in between those reads? I imagine three reads would terminate the effect and four reads would enable the effect again?
Two reads without conflicting reads in between. There is no time limit.
More than two reads has no effect.
Post by Anthony Ortiz
3) What constitutes High RAM being enabled? Is it when either HIRAMRD or HIRAMWRT is enabled, or if both are enabled? I ask because on page 130 Sathers states that ALTZP depends on High RAM being enabled to switch over $D000-$FFFF.
Any combination of those, depending on your intended use.
Post by Anthony Ortiz
4) Is there a particular reason why we need to have HIRAMRD and HIRAMWRT? Why not just have a HIRAM switch that gives you full access when it's set just like any other region of RAM? Is this a feature or the result of some historical oddity?
Because you might not want people to write to it. i.e. have it behave like ROM but contain something different, like integer Basic.
Post by Anthony Ortiz
5) On page 128 Sather's states : "4. When a system reset occurs, all MMU soft switches are reset (turned off). High RAM is disabled for reading and enabled for writing." I was scratching my head wondering why HIRAMWRT' would be enabled after a reset when I realized it's not... I keep forgetting the ['] after HIRAMWRT'. Anyway, my question is, does this mean that when I write to a ROM address it's actually writing to High RAM behind the scenes?
Yes.
Anthony Ortiz
2017-08-24 02:51:33 UTC
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Post by qkumba
Post by Anthony Ortiz
1) What is meant by odd and even access?
The low bit of Address is 1 or 0 (e.g. C089 vs C088).
Post by Anthony Ortiz
2) Double reads - does that mean two consecutive reads, as in I can't even place a NOP in between those reads? I imagine three reads would terminate the effect and four reads would enable the effect again?
Two reads without conflicting reads in between. There is no time limit.
More than two reads has no effect.
Post by Anthony Ortiz
3) What constitutes High RAM being enabled? Is it when either HIRAMRD or HIRAMWRT is enabled, or if both are enabled? I ask because on page 130 Sathers states that ALTZP depends on High RAM being enabled to switch over $D000-$FFFF.
Any combination of those, depending on your intended use.
Post by Anthony Ortiz
4) Is there a particular reason why we need to have HIRAMRD and HIRAMWRT? Why not just have a HIRAM switch that gives you full access when it's set just like any other region of RAM? Is this a feature or the result of some historical oddity?
Because you might not want people to write to it. i.e. have it behave like ROM but contain something different, like integer Basic.
Post by Anthony Ortiz
5) On page 128 Sather's states : "4. When a system reset occurs, all MMU soft switches are reset (turned off). High RAM is disabled for reading and enabled for writing." I was scratching my head wondering why HIRAMWRT' would be enabled after a reset when I realized it's not... I keep forgetting the ['] after HIRAMWRT'. Anyway, my question is, does this mean that when I write to a ROM address it's actually writing to High RAM behind the scenes?
Yes.
Thanks qkumba, this helps a lot!
James Davis
2017-08-23 09:02:59 UTC
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Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Which one of Sather's books are you asking about?

The two books I have:

Understanding the Apple II
Understanding the Apple IIe

do not have page numbers that span the whole book. They have chapter page numbers like 1-1, 2-3, 5-8, etc. So I don't know what book you are referring to.

In my books Sather indicates that the double reads [RR] are equivalent to a write [W], since the latter accesses an address twice (meaning it is put on the address bus twice in rapid succession) like a BASIC POKE. In the A2e firmware listings they use two STA ops with the second one commented, "Twice is nice." The count resets after two: 1,2,0. The 1st read turns on Reading ROM/RAM, the second turns on writing RAM. The latter only works on the odd soft switch addresses (e.g., $C081, $C083, $C085, $C087, $C089, $C08B, $C08D, $C08F) because it involves bits 1 and 3 of the address bus (16 bits wide).

I was just studying all this myself because I am writing an EQUATES file for the Apple IIe with all the things I can find. Something that will never get finished by myself, alone.
Anthony Ortiz
2017-08-23 12:29:10 UTC
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Post by James Davis
Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Which one of Sather's books are you asking about?
Understanding the Apple II
Understanding the Apple IIe
do not have page numbers that span the whole book. They have chapter page numbers like 1-1, 2-3, 5-8, etc. So I don't know what book you are referring to.
Understanding the Apple IIe. You're right, I ordered a copy from India that is a hardcover printed version of a scanned copy and it has page numbers. In my case, page 128 = 5-23
Post by James Davis
In my books Sather indicates that the double reads [RR] are equivalent to a write [W], since the latter accesses an address twice (meaning it is put on the address bus twice in rapid succession) like a BASIC POKE. In the A2e firmware listings they use two STA ops with the second one commented, "Twice is nice." The count resets after two: 1,2,0. The 1st read turns on Reading ROM/RAM, the second turns on writing RAM. The latter only works on the odd soft switch addresses (e.g., $C081, $C083, $C085, $C087, $C089, $C08B, $C08D, $C08F) because it involves bits 1 and 3 of the address bus (16 bits wide).
I was just studying all this myself because I am writing an EQUATES file for the Apple IIe with all the things I can find. Something that will never get finished by myself, alone.
In that case you'll like the "What's where in the Apple" book to go along with Sathers. I'm making a visual representation of the memory map based on the different switch configurations so I'll pass it along when I'm done.
James Davis
2017-08-24 07:06:37 UTC
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Post by Anthony Ortiz
Post by James Davis
Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Which one of Sather's books are you asking about?
Understanding the Apple II
Understanding the Apple IIe
do not have page numbers that span the whole book. They have chapter page numbers like 1-1, 2-3, 5-8, etc. So I don't know what book you are referring to.
Understanding the Apple IIe. You're right, I ordered a copy from India that is a hardcover printed version of a scanned copy and it has page numbers. In my case, page 128 = 5-23
Post by James Davis
In my books Sather indicates that the double reads [RR] are equivalent to a write [W], since the latter accesses an address twice (meaning it is put on the address bus twice in rapid succession) like a BASIC POKE. In the A2e firmware listings they use two STA ops with the second one commented, "Twice is nice." The count resets after two: 1,2,0. The 1st read turns on Reading ROM/RAM, the second turns on writing RAM. The latter only works on the odd soft switch addresses (e.g., $C081, $C083, $C085, $C087, $C089, $C08B, $C08D, $C08F) because it involves bits 1 and 3 of the address bus (16 bits wide).
I was just studying all this myself because I am writing an EQUATES file for the Apple IIe with all the things I can find. Something that will never get finished by myself, alone.
In that case you'll like the "What's where in the Apple" book to go along with Sathers. I'm making a visual representation of the memory map based on the different switch configurations so I'll pass it along when I'm done.
Anthony,

Yes, I have WWA #1, #2, and #3, but not #4. #1 and #2 are more relative to the Apple II and II Plus. #3 has more about the Apple IIe, but mostly in an appendix; otherwise, it is just a combined #1 and #2. (#'s are from the CSA2 WWA thread I started a couple of weeks ago.)

I also recommend using the Apple IIe Technical Reference Manual in conjunction with reading/studying Jim Sather's book. Some of his ideas are better illustrated in the charts (and text) of the Apple IIe T.R.M. than in his charts.

I too have trouble understanding some of JS's MMU soft switch info.

James Davis
Michael J. Mahon
2017-08-23 22:00:33 UTC
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Post by James Davis
Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Which one of Sather's books are you asking about?
Understanding the Apple II
Understanding the Apple IIe
do not have page numbers that span the whole book. They have chapter
page numbers like 1-1, 2-3, 5-8, etc. So I don't know what book you are referring to.
In my books Sather indicates that the double reads [RR] are equivalent to
a write [W], since the latter accesses an address twice (meaning it is
put on the address bus twice in rapid succession) like a BASIC POKE. In
the A2e firmware listings they use two STA ops with the second one
commented, "Twice is nice."
<snip>

Many //e soft switches are sensitive to read vs. write accesses, so no
equivalence between LOADs and STOREs exists.

For most ][ and ][+ soft switches, the only thing that matters is an
access, read or write, so LOADs or STOREs may be used. However, only
absolute indexed "sta abs,x" and indirect indexed "sta (zp),y" STOREs
access the target address twice. This is shown clearly on page 4-23 of
"Understanding the Apple//e".

It is a popular misconception that all STOREs make double accesses, perhaps
contributed to by generalizing from POKE, which does an indexed STORE, to
all STOREs.

The read-modify-write instructions (e.g.: asl) usually do *three* accesses
to their memory locations (and a spurious read to the previous page if
indexing causes a page crossing).

Multiple accesses are important for "toggling" soft switches, like the
speaker and cassette outputs, since they toggle twice, creating a 1 usec
pulse rather than a persistent state change. This is why BASIC users are
told to use PEEK to click the speaker rather than POKE. Assembly language
programmers often use sta $C030 to toggle the speaker, since it preserves
the content of the A register.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
James Davis
2017-08-24 06:43:49 UTC
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Post by Michael J. Mahon
Post by James Davis
Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Which one of Sather's books are you asking about?
Understanding the Apple II
Understanding the Apple IIe
do not have page numbers that span the whole book. They have chapter
page numbers like 1-1, 2-3, 5-8, etc. So I don't know what book you are referring to.
In my books Sather indicates that the double reads [RR] are equivalent to
a write [W], since the latter accesses an address twice (meaning it is
put on the address bus twice in rapid succession) like a BASIC POKE. In
the A2e firmware listings they use two STA ops with the second one
commented, "Twice is nice."
<snip>
Many //e soft switches are sensitive to read vs. write accesses, so no
equivalence between LOADs and STOREs exists.
For most ][ and ][+ soft switches, the only thing that matters is an
access, read or write, so LOADs or STOREs may be used. However, only
absolute indexed "sta abs,x" and indirect indexed "sta (zp),y" STOREs
access the target address twice. This is shown clearly on page 4-23 of
"Understanding the Apple//e".
It is a popular misconception that all STOREs make double accesses, perhaps
contributed to by generalizing from POKE, which does an indexed STORE, to
all STOREs.
The read-modify-write instructions (e.g.: asl) usually do *three* accesses
to their memory locations (and a spurious read to the previous page if
indexing causes a page crossing).
Multiple accesses are important for "toggling" soft switches, like the
speaker and cassette outputs, since they toggle twice, creating a 1 usec
pulse rather than a persistent state change. This is why BASIC users are
told to use PEEK to click the speaker rather than POKE. Assembly language
programmers often use sta $C030 to toggle the speaker, since it preserves
the content of the A register.
--
-michael - NadaNet 3.1 and AppleCrate II: http://michaeljmahon.com
WOW Michael,

You really misunderstood what I said!

I did not say that JS said "two reads are equivalent to a write." I said he indicates it (that is, in some of his charts and tables). And, I am talking about BASIC's Peek and Poke. For assembly, I said two STA ops are used in the IIe firmware listings (which accesses the address twice for the desired effect).

James Davis
Nick Westgate
2017-08-30 05:04:34 UTC
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Post by James Davis
WOW Michael,
You really misunderstood what I said!
Well, what you said is ambiguous and thus open to interpretation, including the common misinterpretation of the ambiguous warning that Apple has put in its manuals. People often claim that STA abs performs two accesses, which is false.
Post by James Davis
double reads [RR] are equivalent to a write [W], since the latter accesses an address twice (meaning it is put on the address bus twice in rapid succession) like a BASIC POKE
AppleSoft POKE is safe on a 65C02. Only one access occurs.
Post by James Davis
The count resets after two: 1,2,0
That is not correct. Even after all these years the LC is tricky. ; - )

Cheers,
Nick.

Brian Patrie
2017-08-25 09:35:53 UTC
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only absolute indexed "sta abs,x" and indirect indexed "sta (zp),y"
STOREs access the target address twice.
I'm glad that this came up, as i've been amongst those mislead into
thinking that this applied to all writes.
Zellyn
2017-08-25 16:47:01 UTC
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Post by Anthony Ortiz
Going through Sather's book and have a few questions...
Out of curiosity, are you aiming to implement an emulation, or write software for the IIe? If you're aiming to write an emulation, you can just run my a2audit program until it passes, and there's a decent chance you got it right! :-)

https://github.com/zellyn/a2audit

Zellyn
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