Any idea what does the Zipchip do with the apple II bus when it's running code that's 100% in its cache?
For example: loop jmp loop , after 3 sync read cycles from the MLB's RAM that code runs 100% off the cache, but the MLB cycles continue... what does the Zipchip put on the Apple II bus then? Reads? Writes? To where?
Any write to a memory location is synchronized with the Apple II memory. This is accomplished by the ZIP-ASIC and may even be buffered (but I doubt that). Sadly the ZIP-Chip ASIC has not been analyzed yet. Here are high resolution DIE shots: https://drive.google.com/open?id=0B5SAWSGa49rLamJSZTloVkphQjA
Sounds like a job for Carte Blanche (I or II) People.
We have the opportunity for another Carte Blanche II run. Would anyone be interested?
This time it would be just the board only (exactly the same version as last time), and the target price would be around US$195 plus shipping.
Anyway, it would be great to hear what you think.