How does the ZIP chip work?

[Eric]

I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.

But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.

If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.

But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

[Michael J. Mahon]

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

The Zip Chip is a processor-cache-bus interface multi-chip module.

It runs at its own speed until either a cache miss occurs on a
memory read or a memory write occurs. For those activities it
must synchronize with the Apple clock and wiggle the processor
wires appropriately.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[sicklittlemonkey]

Post by Eric
What am I missing here?

Nothing. It must have had a cache, and did. ;-)
Early accelerator cards cached all of RAM, I think.
Apple copied the ZIP design for the //c+. (Right guys?)

What I would like to know is the write-back policy for the cache.
I'm guessing that graphics writes were propagated immediately.
That could be tested by running some code in displayed memory.

Cheers,
Nick.

[Michael J. Mahon]

Post by sicklittlemonkey

Post by Eric
What am I missing here?

Nothing. It must have had a cache, and did. ;-)
Early accelerator cards cached all of RAM, I think.
Apple copied the ZIP design for the //c+. (Right guys?)
What I would like to know is the write-back policy for the cache.
I'm guessing that graphics writes were propagated immediately.
That could be tested by running some code in displayed memory.

It's a strict write-through cache. This is necessary since the
tag RAM does not contain "dirty" bits.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Jorge Chamorro Bieling]

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

[Michael J. Mahon]

Post by Jorge Chamorro Bieling

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.

Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.

The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Bryan Parkoff]

Post by Michael J. Mahon

Post by Jorge Chamorro Bieling

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.
The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,

Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run at
14MHz without using accelerator? Let say 14,318,180 crystal osc is on
motherboard. Video scanner depends on 14M crystal osc chip to run at 1MHz
and RAM runs at 2MHz. We may change the logic on the motherboard so CPU
will run at 14MHz while "load/shift bit for video" is performed at the same
time. We can add switch like dip box to switch from 14MHz to original 1MHz.
Cache and internal memory like Zip chip or Transwarp card may not be needed.
Do you expect that it will work if we modify the logic on the
motherboard to manipulate 14M crystal osc chip?

Bryan Parkoff

[Michael J. Mahon]

Post by Bryan Parkoff

Post by Michael J. Mahon

Post by Jorge Chamorro Bieling

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.
The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,
Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run at
14MHz without using accelerator? Let say 14,318,180 crystal osc is on
motherboard. Video scanner depends on 14M crystal osc chip to run at 1MHz
and RAM runs at 2MHz. We may change the logic on the motherboard so CPU
will run at 14MHz while "load/shift bit for video" is performed at the same
time. We can add switch like dip box to switch from 14MHz to original 1MHz.
Cache and internal memory like Zip chip or Transwarp card may not be needed.
Do you expect that it will work if we modify the logic on the
motherboard to manipulate 14M crystal osc chip?

No. The entire timing design of the Apple II is predicated on the
processor interface running at 1MHz. That's why all accelerators
that run using the processor interface do so with caching and bus
synchronization logic. Any time they interface with the Apple II,
they do so at the 1MHz speed.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Bryan Parkoff]

Post by Michael J. Mahon

Post by Bryan Parkoff

Post by Michael J. Mahon

Post by Jorge Chamorro Bieling

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.
The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,
Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run
at 14MHz without using accelerator? Let say 14,318,180 crystal osc is on
motherboard. Video scanner depends on 14M crystal osc chip to run at
1MHz and RAM runs at 2MHz. We may change the logic on the motherboard so
CPU will run at 14MHz while "load/shift bit for video" is performed at
the same time. We can add switch like dip box to switch from 14MHz to
original 1MHz. Cache and internal memory like Zip chip or Transwarp card
may not be needed.
Do you expect that it will work if we modify the logic on the
motherboard to manipulate 14M crystal osc chip?

No. The entire timing design of the Apple II is predicated on the
processor interface running at 1MHz. That's why all accelerators
that run using the processor interface do so with caching and bus
synchronization logic. Any time they interface with the Apple II,
they do so at the 1MHz speed.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,

Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design? It does not make sense because it can handle maximum 14MHz
like WDC 65816 CPU chip. Nintendo NES and sNES run at approximately less
than 2MHz. Apple IIgs with 28M crystal osc runs at 2.5MHz without using
accelerator card. If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Bryan Parkoff

[Eric Smith]

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design?

No, they're limited to 1 MHz due to the Apple II design.

Post by Bryan Parkoff
If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Not if you want your Apple II to actually work. The other logic and
memory chips in the Apple and on peripheral cards are not fast enough,
so nothing would work correctly.

But even if the electronics otherwise worked, you wouldn't get proper
video, because all the timings would be approximately fourteen times too
fast. Your horizontal and vertical sync would be around 220 KHz and
840 Hz, rather than around the required frequencies of 15.75 KHz and 60 Hz.

And even if all that worked, you'd have to rewrite RWTS and any sound
routines.

[Kevin Greene]

Let's say I just upgraded all the components on the motherboard to work
at the faster speed. Assuming that I didn't care about video output
(Any RGB cards work > 1mhz?) or floppy drive access (is this only 5 1/4"
that use timing loops? Would any of the 3.5" drives work? Or the CFFA
works I think) could it work?

I suppose at that point you might as well create another 6502 computer
with the apple ROM.

Post by Eric Smith

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design?

No, they're limited to 1 MHz due to the Apple II design.

Post by Bryan Parkoff
If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Not if you want your Apple II to actually work. The other logic and
memory chips in the Apple and on peripheral cards are not fast enough,
so nothing would work correctly.
But even if the electronics otherwise worked, you wouldn't get proper
video, because all the timings would be approximately fourteen times too
fast. Your horizontal and vertical sync would be around 220 KHz and
840 Hz, rather than around the required frequencies of 15.75 KHz and 60 Hz.
And even if all that worked, you'd have to rewrite RWTS and any sound
routines.

[Michael J. Mahon]

Post by Kevin Greene

Post by Eric Smith

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz
according to the CPU design?

No, they're limited to 1 MHz due to the Apple II design.

Post by Bryan Parkoff
If you rewire 6502 CPU to 14M crystal osc by modifying timing logic,
it might work without accelerator card.

Not if you want your Apple II to actually work. The other logic and
memory chips in the Apple and on peripheral cards are not fast enough,
so nothing would work correctly.
But even if the electronics otherwise worked, you wouldn't get proper
video, because all the timings would be approximately fourteen times too
fast. Your horizontal and vertical sync would be around 220 KHz and
840 Hz, rather than around the required frequencies of 15.75 KHz and 60 Hz.
And even if all that worked, you'd have to rewrite RWTS and any sound
routines.

Let's say I just upgraded all the components on the motherboard to work
at the faster speed. Assuming that I didn't care about video output
(Any RGB cards work > 1mhz?) or floppy drive access (is this only 5 1/4"
that use timing loops? Would any of the 3.5" drives work? Or the CFFA
works I think) could it work?

A few things might work, but not many. Almost every peripheral for
the Apple II counts on the timing of the Apple bus and the frequency
of the clocks. And, of course, they are designed with logic that
doesn't run well at 14MHz.

BTW, you *have* to care about the video, since it's the only way
to see what an Apple II is doing! RGB cards just change the color
coding, not the scan standards that are set by the main board.

Post by Kevin Greene
I suppose at that point you might as well create another 6502 computer
with the apple ROM.

Now you've got it.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Bryan Parkoff]

Post by Eric Smith

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design?

No, they're limited to 1 MHz due to the Apple II design.

Post by Bryan Parkoff
If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Not if you want your Apple II to actually work. The other logic and
memory chips in the Apple and on peripheral cards are not fast enough,
so nothing would work correctly.
But even if the electronics otherwise worked, you wouldn't get proper
video, because all the timings would be approximately fourteen times too
fast. Your horizontal and vertical sync would be around 220 KHz and
840 Hz, rather than around the required frequencies of 15.75 KHz and 60 Hz.
And even if all that worked, you'd have to rewrite RWTS and any sound
routines.

Eric,

Well, I mean that timing remains unchanged for video and RAM which they
run at 1MHz for video and 2MHz for RAM. TV will always be the same as
horizontial 15KHz and vertical 60Hz. The fact is that first cycle of 14M
responds to video scanner and 6502 CPU before it begins to suspend or delay
until 15th cycle of 14M. If you redesign the timing which it allows 6502
CPU to run each cycle of 14M without delay, 6502 CPU will run at 14MHz while
video scanner and RAM stay at the same speed of 1MHz and 2MHz.
Michael Mahon said that it is impossible because data will be wrong when
it is read or writen to the RAM.

Bryan Parkoff

[h***@freenet.de]

I'm certainly not here to criticize anyone - especially not one with
some rather creative ideas - but I strongly recommend that you read one
or both of the following excellent books to better understand the
hardware you are dealing with:

"Understanding the Apple II" by Jim Sather
"The Apple II Circuit Description" by Winston D. Gayler

bye
Marcus

[Bryan Parkoff]

Post by h***@freenet.de
I'm certainly not here to criticize anyone - especially not one with
some rather creative ideas - but I strongly recommend that you read one
or both of the following excellent books to better understand the
"Understanding the Apple II" by Jim Sather
"The Apple II Circuit Description" by Winston D. Gayler
bye
Marcus

Marcus,

Thank you. I have Understanding the Apple II + //e" manual already.
Try to imagine if you replace ROM and RAM chips to support 4MHz instead of
2MHz. You will be able to run 6502 CPU at 2MHz on Apple II+ while video is
still running at 14M with no problem. It would affect Disk II, sound, and
slots. I have no idea if video scanner is affected that it is supposed to
access RAM at 2MHz. You imagine that it may not work! It is like a hack
without using accelerator card.

Bryan Parkoff

[Michael J. Mahon]

Post by Bryan Parkoff

Post by h***@freenet.de
I'm certainly not here to criticize anyone - especially not one with
some rather creative ideas - but I strongly recommend that you read one
or both of the following excellent books to better understand the
"Understanding the Apple II" by Jim Sather
"The Apple II Circuit Description" by Winston D. Gayler
bye
Marcus

Marcus,
Thank you. I have Understanding the Apple II + //e" manual already.
Try to imagine if you replace ROM and RAM chips to support 4MHz instead of
2MHz. You will be able to run 6502 CPU at 2MHz on Apple II+ while video is
still running at 14M with no problem. It would affect Disk II, sound, and
slots. I have no idea if video scanner is affected that it is supposed to
access RAM at 2MHz. You imagine that it may not work! It is like a hack
without using accelerator card.

Apple accelerated the Apple II twice--once in the IIc+ with a Zip Chip
clone design, and once in the IIgs with shadow RAM. Preserving the
compatibility that makes a hack interesting imposes many constraints
that keep it from being simple.

The Apple II is a remarkably clever intertwining of constraints and
capabilities that achieved unprecedented "bang for the buck" when it
was designed. Ironically, that very cleverness makes it much more
difficult to just "speed up the clock" and still have an Apple II.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[David Wilson]

Post by Michael J. Mahon
The Apple II is a remarkably clever intertwining of constraints and
capabilities that achieved unprecedented "bang for the buck" when it
was designed. Ironically, that very cleverness makes it much more
difficult to just "speed up the clock" and still have an Apple II.

Indeed. My OSI Superboard II was a doddle to accelerate. The way it
handled the video chain and the CPU both needing access to the video
RAM was to give the CPU priority. Any time the CPU read from or wrote
to the screen, a short black line appeared.
Speeding up the processor had the advantage of reducing the length of
these black lines.
More amusing was to load a program into VRAM and run it - the video
display would be covered in black lines.

[Kevin Greene]

Post by Michael J. Mahon
Apple accelerated the Apple II twice--once in the IIc+ with a Zip Chip
clone design, and once in the IIgs with shadow RAM. Preserving the
compatibility that makes a hack interesting imposes many constraints
that keep it from being simple.

I'm curious if anyone has tried to copy the IIc+ zip chip design...since
there were a few discrete components perhaps this would be a
possibility? I know there was a PLA or something, is there a way to
read the one in the IIc+ to copy it? (I know some are copy protected.)

[Michael J. Mahon]

Post by Bryan Parkoff

Post by Eric Smith

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design?

No, they're limited to 1 MHz due to the Apple II design.

Post by Bryan Parkoff
If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Not if you want your Apple II to actually work. The other logic and
memory chips in the Apple and on peripheral cards are not fast enough,
so nothing would work correctly.
But even if the electronics otherwise worked, you wouldn't get proper
video, because all the timings would be approximately fourteen times too
fast. Your horizontal and vertical sync would be around 220 KHz and
840 Hz, rather than around the required frequencies of 15.75 KHz and 60 Hz.
And even if all that worked, you'd have to rewrite RWTS and any sound
routines.

Eric,
Well, I mean that timing remains unchanged for video and RAM which they
run at 1MHz for video and 2MHz for RAM. TV will always be the same as
horizontial 15KHz and vertical 60Hz. The fact is that first cycle of 14M
responds to video scanner and 6502 CPU before it begins to suspend or delay
until 15th cycle of 14M. If you redesign the timing which it allows 6502
CPU to run each cycle of 14M without delay, 6502 CPU will run at 14MHz while
video scanner and RAM stay at the same speed of 1MHz and 2MHz.
Michael Mahon said that it is impossible because data will be wrong when
it is read or writen to the RAM.

Just for the record, I didn't say it would be "wrong". I said
that there are only two memory access slots per microsecond, and
only one is available to the processor.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Linards Ticmanis]

Post by Bryan Parkoff
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design? It does not make sense because it can handle maximum 14MHz
like WDC 65816 CPU chip. Nintendo NES and sNES run at approximately less
than 2MHz. Apple IIgs with 28M crystal osc runs at 2.5MHz without using
accelerator card. If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

The RAM on the Mainboard can't run at 14MHz. The ROM probably can't
either. Most peripheral cards can't run at 14MHz. etc.

What you want to do amounts to designing a new computer.

[Michael J. Mahon]

Post by Bryan Parkoff

Post by Michael J. Mahon

Post by Bryan Parkoff

Post by Michael J. Mahon

Post by Jorge Chamorro Bieling

Post by Eric
I've been wondoring how the ZIP chip can speed up an Apple IIe. I
understand it has a 4 Mhz 65C02 and it plugs into the original 6502
socket.
But, the original 6502 only has half of each 1 Mhz interval (I'm
rounding to 1 Mhz to make it easier to discuss) to access memory
because the video refresh circuit uses the other half. So, the orig
6502 has a 500ns cycle to access memory.
If the ZIP chip does not have it's own memory (does it?), then it can
only speed up that part of the 1 Mhz cycle that is not used for video
refresh. Assuming main memory could run 4X faster (which it can't),
then it could bring that 500ns down to maybe 125ns. This means the
overall processing (including the obligatory video cycles) would go
from 1000ns to about 625ns, which is less that a 50% speedup.
But main memory can't run any faster, so the zip chip must have some
kind of cache? What am I missing here?

Yes, the zipchip has internal ram. It caches as much as it can. Once in
the cache, it does not need to access the mainboard ram for
reading/fetching/executing, only for writes and only if the write goes
to the screen buffers ot the i/o addresses (of course i/o addresses are
always read from the a2 mainboard). Also, there's a potential problem
with ram expansion cards (whose "pages" overlap the rom addresses) which
are activated using different addresses/schemes so you can tell the
zipchip to enable/disable caching for rom addresses($D000-FFFF). It
seems to me that the $c800-cfff range is also never cached as my videx
does not speed up much. The same goes individually for each slot's rom
addresses because some cards use the slot's rom address for i/o (the
videx screen buffer is a good example of this, starting at $cc00). To
deal with critical timing loops as is the case with diskII i/o, you can
configure it to switch to normal (1MHz) speed for "a while" when
accessing whichever slot (you usually set this only for slot 6). The
last zipchips ran at 8MHz internally..! and it looks like there were
even 10MHz rocketchips (I've never seen one).

No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.
The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,
Is there a possibility that 6502 CPU chip and 65C02 CPU chip can run
at 14MHz without using accelerator? Let say 14,318,180 crystal osc is on
motherboard. Video scanner depends on 14M crystal osc chip to run at
1MHz and RAM runs at 2MHz. We may change the logic on the motherboard so
CPU will run at 14MHz while "load/shift bit for video" is performed at
the same time. We can add switch like dip box to switch from 14MHz to
original 1MHz. Cache and internal memory like Zip chip or Transwarp card
may not be needed.
Do you expect that it will work if we modify the logic on the
motherboard to manipulate 14M crystal osc chip?

No. The entire timing design of the Apple II is predicated on the
processor interface running at 1MHz. That's why all accelerators
that run using the processor interface do so with caching and bus
synchronization logic. Any time they interface with the Apple II,
they do so at the 1MHz speed.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."

Michael,
Do you mean that 6502 / 65C02 CPU chip are limited to 1MHz according to
the CPU design? It does not make sense because it can handle maximum 14MHz
like WDC 65816 CPU chip. Nintendo NES and sNES run at approximately less
than 2MHz. Apple IIgs with 28M crystal osc runs at 2.5MHz without using
accelerator card. If you rewire 6502 CPU to 14M crystal osc by modifying
timing logic, it might work without accelerator card.

Notice I didn't say anything at all about limits on the speed of a
CPU, only limits on the speed at which a CPU can interface with the
Apple--a limit imposed by the Apple II design which was very appropriate
when the Apple II was designed, and around which the entire system was
implemented.

During each cycle (about 1 microsecond), the Apple II memory services
at most two requests--a read from the video generator, and a read or
write from the 65(C)02 CPU. There is no way within the design to
accomodate more than these two memory accesses, since they may even be
to the same location.

As a result, any accelerator must design a mechanism for the faster CPU
of the accelerator to synchronize with the Apple II bus and wait any
response. What allows any accelerator to run faster than the Apple bus
is the presence of fast memory which contains a copy of the Apple RAM
data for the address(es) being referenced by the CPU. This is the
"modified timing logic" that allows acceleration.

The fast CPU can then run at full speed so long as all of its memory
needs are being met by the contents of the fast memory cache. Whenever
it is necessary to get new information from Apple memory, or to send new
data to Apple memory, the fast CPU must synchronize with the Apple bus
(so that it is the CPU's turn to interact with memory) and slow down to
receive or send data.

The effective speed of the fast CPU is the weighted average of its time
running at high speed and its time running at 1MHz while synchronized
with the Apple bus. Except for very special programs, this effective
speed is seldom more than 60%-70% of a Zip Chip's speed. For example,
an 8MHz Zip Chip-equipped machine runs typical software about 5x faster
than stock 1MHz speed, for a 67% speedup.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Eric]

Thanks much for the info! I didn't know it was that sophisticated. I
enjoy playing around with old computers, even though they're not at all
competitive by today's standards.

I'd like to see someone sell a modern version of an apple II, perhaps
implemented using an FPGA. This could be both compatible and very fast.
Gary Becker seems to have a cool project going along these lines:

http://www.applefritter.com/blog/12920

http://www.geocities.com/gary_L_becker/

To get around the ROM license issue it might make sense to make the ROM
images downloadable into RAM, and that way they don't have to
redistribute firmware code that Microsoft may not approve of.

Why doesn't Apple make something like this? It could even be very small
- possibly the same size as an IPOD, not counting the video display. A
small LCD video screen would also be cool - maybe the form factor of a
PocketPC...

Eric

[h***@freenet.de]

Post by Eric
Why doesn't Apple make something like this? It could even be very small
- possibly the same size as an IPOD, not counting the video display. A
small LCD video screen would also be cool - maybe the form factor of a
PocketPC...

Go ahead - ask the company that let the A2-line die in favour of the
Mac and abandon the Newton about economical decisions.

On the other hand: You could run the Apple emulator for the Palm if you
think that an A2 without a keyboard is sexy...

bye
Marcus

[Michael J. Mahon]

Post by h***@freenet.de

Post by Eric
Why doesn't Apple make something like this? It could even be very small
- possibly the same size as an IPOD, not counting the video display. A
small LCD video screen would also be cool - maybe the form factor of a
PocketPC...

Go ahead - ask the company that let the A2-line die in favour of the
Mac and abandon the Newton about economical decisions.

Right. I think it's safe to say that, for a host of reasons ranging
from business to personal, Jobs hates the Apple II.

Post by h***@freenet.de
On the other hand: You could run the Apple emulator for the Palm if you
think that an A2 without a keyboard is sexy...

And there will soon be nice emulators for small keyboarded devices.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."

[Jorge Chamorro Bieling]

Post by Michael J. Mahon
No, the Zip Chip is strictly write-through. All writes slow down
and go to Apple RAM (or whatever). There is no "dirty" bit in the
cache tag RAM. To delay writes would complicate cache misses a
great deal and would have to be defeated in any case for graphics
and I/O addresses, as you note.
Caching is defeated whenever "bank switching" can occur that is
not tracked by the Zip Chip. The I/O expansion ROM area ($C800..
$CFFF) is an example of this. It does, however, track the bank
switching in RamWorks-type expansion cards up to 2MB. This limit
is dictated by the 8-bit x 8K tag ram: 3 bits for upper (64K)
address bits, plus up to 5 bits for RAM card bank. 32 banks of
64K in the AUX slot adds up to 2MB AUX RAM, plus the 64K on the
main board.
The Zip can be configured to slow down to 1MHz (run synchronously)
for several kinds of references. The slot I/O addresses are the
most commonly stated, but the speaker address and the paddle trigger
are a couple of others. When a "slow mode" slot /DEVSEL address is
referenced, the Zip resets an internal 53 millisecond timer. It
resumes accelerated execution when that timer times out.

GREAT. This can be said louder, but not better.

[sicklittlemonkey]

Post by Jorge Chamorro Bieling
GREAT. This can be said louder, but not better.

I agree, although a couple of geeky jokes wouldn't have been amiss.

Michael:
When will you get around to writing "Understanding the Apple //c"? ;-)

Cheers,
Nick.

[Michael J. Mahon]

Post by sicklittlemonkey

Post by Jorge Chamorro Bieling
GREAT. This can be said louder, but not better.

I agree, although a couple of geeky jokes wouldn't have been amiss.
When will you get around to writing "Understanding the Apple //c"? ;-)

Wow--that's quite a compliment!

I'm in awe of the thoroughness and accuracy of Jim Sather.

-michael

Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."